ARM Cortex-M7

⏱ 35h (5 days)

📋 Level 2 (Intermediate)

📍 In-Person Tunis / Online

🎯 Learning Objectives

This course explains the hardware and software architecture of the Cortex-M7 to enable participants to efficiently develop low-level software by implementing the features offered by the CPU: exceptions, low-power modes, MPU, ARMv7-M assembler, and cache maintenance.

📋 Prerequisites and related courses

Prerequisites

Level 2 (Intermediate) — Proficiency in embedded C, STM32 architecture, GCC/GDB toolchain, RTOS basics. Equivalent to the OpCode Labs Firmware Level 2 course or similar professional experience.

🛠 Practical environment

🔧 Hardware Platforms

Based on the ST STM32F7 Discovery board. Each participant has their own board during the training.

💻 IDE & Toolchain

STM32CubeIDE
GCC ARM / GDB / OpenOCD
Logic Analyzer & Oscilloscope

📍 Format & Certification

📍 Location & Format

In-person in Tunis or online (remote with access to a remote lab). Groups of 6–12 participants.

🎓 Certificate of Completion

An OpCode Labs certificate of completion will be issued upon completion of the training.

📚

Detailed program

6-Stage Pipeline

6-stage pipeline, dual-issue, speculative execution, branch prediction.

L1 Cache

D-Cache/I-Cache, politiques write-back/write-through, allocate, opérations de maintenance.

AXI Bus (AMBA4)

AXI vs AHB, transactions burst, outstanding transfers, impact performances.

TCM Memory

ITCM/DTCM, zero wait-state access, code placement and critical data.

MPU

Configuring regions, access permissions, and cache attributes by region.

Exceptions & Low Power

Exceptional model ARMv7-M, tail-chaining, late arrival, WFI/WFE, sleep modes.

ARMv7-M Assembler

Thumb-2 instructions, inline assembly GCC, intrinsics CMSIS, analysis of generated code.

Merge Buffer

Re-ordering problem, bypass strategies, impact on DMA.

Operating Systems

Connectivity & Middleware

Analog & Hardware

Signal Processing

Programming Languages

CPU/MCU Architecture